1. Technical Field
The present invention relates to a semiconductor apparatus, and more particularly, to a power-up signal generation circuit.
2. Related Art
A semiconductor apparatus generates a variety of internal voltages VPERI and VCORE using an external voltage VDD.
The semiconductor apparatus detects whether the above-described voltages approach a predetermined level or not, and generates power-up signals for the respective internal voltages. Accordingly, the semiconductor apparatus performs a reset process and then performs various operations after various circuitry have been reset to a known state.
For example, referring to FIG. 1A, a power-up signal PWRUP may be generated when an internal voltage VPERI approaches a predetermined level, that is, a trigger level (for example, 0.7-0.8V).
At this time, the trigger level corresponds to the level of the internal voltage, at which the power-up signal PWRUP changes.
A minimum level of the internal voltage VPERI is required for performing stable operation in the semiconductor apparatus. The minimum level may be, for example, a target level of 1.35V.
In this case, since the trigger level is lower than the target level of the internal voltage VPERI, it is highly likely that a reset error may occur in the semiconductor apparatus.
Therefore, in order to prevent such an error, the trigger level of the internal voltage VPERI may be increased to 1.1-1.2V, as shown in FIG. 1B.
In this method, however, when the level of the internal voltage VPERI temporarily decreases during normal operation, the is power-up signal PWRUP may be regenerated to reset the semiconductor apparatus.